The main advantage I can see in Chisel, based on a quick review of the documentation is the assertion that it “Generates high-speed C++-based cycle-accurate software simulator”. This could be of value, particularly to someone wishing to develop OOP test-bench frameworks in the same environment as the actual design, without having to spend $$s on an expensive SystemVerilog/VHDL commercial simulator. A RISC-V micro-processor test environment is much more complex than the micro-processor design itself, so having a solid software framework to test it is of value.

People use Chisel because they are dramatically more productive in Chisel than in Verilog, VHDL, or SystemVerilog. It allows them to write RTL code in much higher level of abstraction, while still controlling exactly what flops and gates are being generated.